The present invention relates to a semiconductor device and, more particularly, to a device which receives a plurality of power supply voltages.
Semiconductor devices include one in which the power supply of an input interface circuit is suppressed in order to suppress the power consumption of an MPU (Micro Processor Unit), a CPU (Central Processor Unit), or another logic circuit connected to this semiconductor device. This semiconductor device comprises an internal circuit which operates by an internal signal having a voltage swing width different from that of an input signal. In this device, the first power supply voltage having the same level as that of the input signal, and the second power supply voltage having the same level as that of the internal signal are respectively applied for an input circuit for receiving the input signal, and the internal circuit for performing processing upon reception of an output from the input circuit. FIG. 11 shows the arrangement of a semiconductor device 10 associated with the present invention.
The semiconductor device 10 comprises an input buffer circuit 21, an internal circuit 22, an output buffer circuit 23, and a substrate bias generator 33. The semiconductor device 10 further comprises an input pad 31, power supply lines 32, 34, and 36, ground pads 35 and 37, an output pad 38, and a substrate bias voltage line 71. A power supply voltage V.sub.DDI equal to the voltage of an input signal is applied to the power supply line 32, a substrate bias voltage V.sub.BB is applied to the substrate bias voltage line 71, a power supply voltage V.sub.DD equal to the voltage of an internal signal is applied to the power supply line 34, and a power supply voltage V.sub.DDQ equal to the voltage of a signal to be externally output is applied to the power supply line 36. The power supply voltages V.sub.DDI and V.sub.DDQ are as low as, e.g., 1.8 V or 2.5 V. The power supply voltage V.sub.DD is higher, e.g., 3.3 V or 5 V. Both the power supply voltages V.sub.DDQ and V.sub.DDI are for interfaces and generally at the same level.
The semiconductor device 10 has the ground pads 35 and 37. A ground terminal 42 of the internal circuit 22 larger in charge/discharge current than the input buffer circuit 21 is connected to the ground pad 35 via a ground line 52 having a large line width. A ground terminal 41 of the input buffer circuit 21 is connected to the ground pad 35 via a ground line 51 having a small line width and a parasitic resistance R higher than the resistance of the ground line 52. The voltage of the ground line 51 is a ground voltage V.sub.SSI. A ground terminal 43 of the output buffer circuit 23 is connected to the ground pad 37 via a ground line 53 having a large line width.
The input buffer circuit 21 is equivalent to the first stage of the input portion of the semiconductor device 10, and receives an input signal externally input via the input pad 31. The power supply voltage V.sub.DDI is applied to the input buffer circuit 21 via the power supply line 32.
The internal circuit 22 receives the input signal output from the input buffer circuit 21. The power supply voltage V.sub.DD is applied to the internal circuit 22 via the power supply line 34. The internal circuit 22 amplifies and converts the input signal swinging within the range of the power supply voltage V.sub.DDI to a ground voltage V.sub.SS into an internal signal swinging within the range of the power supply voltage V.sub.DD to the ground voltage V.sub.SS, and then performs necessary processing. The internal circuit 22 outputs the internal signal swinging within the range of the power supply voltage V.sub.DD to the ground voltage V.sub.SS. When the semiconductor device 10 is, e.g., a semiconductor memory device, the internal circuit 22 comprises a memory array, a decoder, a sense amplifier, and various control circuits.
The power supply voltage V.sub.DDQ is applied to the output buffer circuit 23 via the power supply line 36. The output buffer circuit 23 receives the internal signal output from the internal circuit 22 to output a signal swinging within the range of the power supply voltage V.sub.DDQ to the ground voltage V.sub.SS. This signal is output outside the device 10 via the output pad 38. Of the circuits 21 to 23, the power consumption of the internal circuit 22 is large. A power supply line 62 connected to the power supply line 34, and the ground line 52 connected to the ground pad 35 have large widths. The power consumption of the output buffer circuit 23 is also large. Similarly, a power supply line 63 connected to the power supply line 36, and the ground line 53 connected to the ground pad 37 have large widths. The power consumption of the input buffer circuit 21 is the smallest. A power supply line 61 connected to the power supply line 32, and the ground line 51 connected to the ground pad 35 have small widths.
A small line capacitance of power supply lines leads to a small effect of stabilizing the power supply voltage. If a power supply voltage having fluctuations is applied from a power supply outside the device 10, the fluctuations cannot be satisfactorily suppressed. Therefore, upon application of the power supply voltage having fluctuations, the device 10 may malfunction.
Particularly, the power supply line 61 connected to a circuit like the input buffer circuit 21 which is often formed in a well independently of the remaining circuits 22 and 23 is much smaller in capacitance than the power supply lines 62 and 63. Since the input buffer circuit 21 is located on the first stage where an input signal is externally input, a malfunction of the circuit 21 influences all subsequent processes. For this reason, the input buffer circuit 21 must be particularly prevented from malfunctioning.
FIG. 12 shows the arrangement of another semiconductor device associated with the present invention. In this device, to prevent an input buffer circuit 21 from malfunctioning, a capacitance in addition to a parasitic capacitance is formed on a power supply line 32 for supplying the power supply voltage V.sub.DDI to the circuit 21. In many cases, a parasitic capacitance exists between the power supply line 32, and another power supply line 34 or 36 or a ground pad 35 or 37. However, only this parasitic capacitance cannot satisfactorily suppress fluctuations in power supply voltage, so a capacitance C0 is connected between the power supply line 32 and the ground pad 35.
A ground line 52 having a large line width and a low parasitic resistance is connected between the ground pad 35 and an internal circuit 22. The power consumption of the internal circuit 22 is large, and the ground voltage V.sub.SS varies in turning on/off a transistor constituting the internal circuit 22. The variations in ground voltage V.sub.SS are transmitted to the power supply line 32 via the ground line 52, the ground pad 35, and the capacitance C0. That is, although the capacitance of the power supply line 32 can be increased to suppress fluctuations in power supply voltage by arranging the capacitance C0, variations in power supply of the internal circuit 22 connected to the capacitance C0 are transmitted to cause a malfunction of the input buffer circuit 21.
FIGS. 13A and 13B respectively show variations in power supply voltage V.sub.DD and ground voltage V.sub.SS. Assume that the power supply voltage V.sub.DD applied to the power supply line 34 varies to the negative side, and the ground voltage V.sub.SS to the ground pad 35 varies to the positive side, as shown in FIG. 13A. The variations in ground voltage V.sub.SS in the ground pad 35 are transmitted to the power supply line 32 via the capacitance C0. At this time, the power supply voltage V.sub.DDI varies to the positive side by level L1, as shown in FIG. 13B. As a result, when a high-level (H) input signal is input, as shown in FIG. 13B, the input buffer circuit 21 may malfunction. That is, if the power supply voltage V.sub.DDI varies to the positive side by level L1, the circuit threshold Vth of the input buffer circuit 21 increases by Vth+L1. Accordingly, even when an input signal of a level higher than the original threshold Vth is input, if the level of the input signal is lower than the circuit threshold Vth+L1, the circuit recognizes the input signal to be at low level.